When using verification components (VVCs) in UVVM, you can see all the transaction in the wave-view of the simulator. This allows a very good overview of all the transactions on the various interfaces - and is much easier to understand than watching the actual DUT interface signals.
In the figure above, you can easily see that the PIF_VVC (Processor Interface VVC) is executing a register write to the TX_DATA register, and immediately following that the UART VVC starts looking for the generated UART frame. In fact the uart_expect() command could be issued at the same time as the pif_write(), but is delayed in this example just to see the sequence of events.
In the figure you can also see that the UART VVC initiates a transmission towards the DUT at the same time as the pif_write(). Then after the transmission is completed, a pif_check() command is issued to check that the right data was received.
The transactions can be seen in the simulators by including the shared variable record 'transaction_info', which is defined for every VVC.
Real life snapshots of wave views are shown below - for the same transactions, but shown differently.
All transaction info and actual interface signals
All transaction info only
Collapsed transaction info only