UVVM VVC Framework

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UVVM - VHDL Verification Component (VVC) Framework

Open source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC. Yields a System/Framework and methodology for building a structured, component oriented testbench architecture. 

UVVM gives you the most modular and best VHDL testbench architecture available today.



UVVM - Version v2.2 (April 2017)

May be downloaded directly from GitHub or via the Github zip-file generator

New in this version: 

  • Multicast (Sending commands to all instances or channels of a given VVC type)
  • Broadcast (Sending commands to all VVCs in your TB)
  • VVC dedicated values for fetch instructions from sequencer
  • await_any_completion() to wait for just the first out of many selected VVC completions
  • Multiple central sequencers
    It is now possible to access any combination of VVCs – or even the same VVC – from different central sequencers.
    (We still recommend to have a single central sequencer, but for some special cases multiple sequencers may be the best alternative)
  • Synchronization between different VHDL processes
    - one or many processes waiting for one process to reach a certain point (could be used anywhere, but typically between central sequencers or local sequencers)
    - barrier synchronisation (where all involved processes must wait until all involved process have reached a certain point)



  • VVC Framework & Utility Library
  • Various VHDL Verification components (VVCs)
    (UART, AXI3-lite, SBI, I2C, Avalon MM, AXI3-stream, SPI)
  • Support for automatic generation of new VVCs (yields almost complete VVC)
  • Easy to understand Scheduler to control VVCs
  • Great testbench overview and coordination 


Open Source.  MIT license


Note: You need Modelsim 10.3c or Riviera-PRO 2015.10.85 - or newer, due to VHDL 2008 compatibility. 


'A game changer for VHDL verification: - Advanced VHDL Verification - Made simple - For anyone' 

This presentation from FPGA Kongress in Munich (Germany) in July 2016 shows how advanced verification with good functional coverage can be achieved in a very structured manner with a proper testbench architecture.

UVVM VVC Framework is the best approach available for making structured testbenches for medium to high complexity testbenches in VHDL.

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'Advanced VHDL Verification - Made simple - For anyone' 

three-part post on LinkedIn as a simple introduction to why UVVM is the best VHDL testbench methodology available.

Due to popular demand we have now made them directly available here:

- Part 1: The testbench architecture

Part 2: The testbench sequencer

Part 3: The VHDL Verification Component (VVC)



New info:

- Transaction viewing in UVVM 

- Efficient reuse using VVCs


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