There will be three presentations and two hands-on tutorial from Bitvis at FPGA-Congress in Munich in Germany July 11-13, 2017. (2+2 of these will be on UVVM - Universal VHDL Verification Methodology)
July 12: 'UVVM in a nutshell - An introduction to making good VHDL testbenches.
- Case 1: Building a complete VHDL testbench architecture for a UART in 30 minutes:'
- Case 2: Finding value and cycle related bugs in a DUT – using UVVM VHDL verification components.
See program and abstracts here
FPGA-Kongress is one of the largest FPGA conferences in the world.
We are really proud that three presentations and two tutorials have been accepted :-)
FPGA design : Bugs and Problems – And how to avoid them
As a consultant we see lots of different projects in many companies; - sometimes as a designer, and sometimes just helping out with implementation, verification, debug or review. This presentation will give an overview of the worst project and product consequences with respect to both bugs and delays. The worst sources of these bugs and delays will then be presented and analysed, and finally some general remedies are proposed.
Making an advanced Bus Functional Model (BFM) from scratch
Everybody uses BFMs (or procedures) for accessing the DUT (Device Under Test) interfaces from their VHDL testbench. E.g. using a procedure like avalon_mm_write(C_ADDR, C_DATA) rather than wiggling the Avalon MM signals every time an Avalon MM write access is need. This approach is very common as it significantly improves readability, maintainability and reuse, and thus of course results in a better quality FPGA and reduced development time. Unfortunately however, most BFMs include only the pin wiggling, sampling and result comparison, - whereas adding a bit more functionality would in fact increase the value of these procedures significantly.
Some very useful extensions would be a) synchronization to the clock, b) normalisation and sanity check of the procedure parameters, c) alert handling and mismatch report for unexpected behaviour, d) logging of the result – with verbosity control, e) configuration of allowed interface behaviour, etc.
This presentation will show how to build a BFM from scratch, first handling the DUT interface only, and then extending the procedure with very useful added functionality.
UVVM – Universal VHDL Verification Methodology – The standardised VHDL testbench architecture
For an FPGA design we all know that the architecture – all the way from the top to the micro architecture – is critical for both the FPGA quality and the development time.
It should really be obvious that this also applies to the testbench.
Most FPGA designs are split into stand-alone modules – for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities (components), and they are normally accessed from a CPU via a more or less standardised bus interface (register interface). The software running on that CPU does of course not need to know anything about the implementation of the modules (say a UART) or its interface protocol. All the software needs to know is the functionality of the control and status registers it can access (e.g. writing to the UART_TX register). This abstraction allows a safe and very efficient control of the complete FPGA. It is pretty obvious that this approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse. UVVM provides a very simple and powerful architecture for this – to allow designers to build their own test harness much faster than ever before –nusing a mix of their own and open source verification components. OSVVM may be used seamlessly with UVVM, so that Constrained Random and Functional Coverage may be combined with a great architecture and infrastructure, and controlled in an easily understandable, maintainable and reusable way.
This presentation will show you how simple this is to understand, build and control
Overview, readability, maintainability, extensibility and reuse are all key to efficient and good verification, but for most testbenches not many of these critical parameters are even close to satisfied. UVVM provides a very simple and powerful architecture that promotes all of these critical parameters, and thus also allows designers to build their own test harness much faster than ever before. In this hands-on tutorial you will experience the simplicity of making a full test harness from scratch when using easy to understand reusable infrastructure and verification components. This will show you the best way to implement any medium to high complexity VHDL testbench - independent of methodology, libraries and tools, - but using the standardised VHDL Verification Component approach provided by UVVM automatically provides the best possible Overview, Readability, Maintainability, Extensibility and Reuse (Case 1 and Case 2 are independent tutorials. You may register for any one or both)
(Case 1 and case 2 are independent tutorials. Hence you don’t need to have done Case 1 to do Case 2.)
The same critical parameters as in Case 1 do of course always apply.
In this hands-on tutorial you will see
1. How to make the reusable verification component even more valuable by adding some very useful features
2. How to combine with and control Randomisation and Functional Coverage from OSVVM
3. How to control skewing of interface accesses with respect to each other in order to detect cycle related bugs
This is a great opportunity to get a taste of this improved way of writing good testbenches – and to experience the simplicity and the overview you get with UVVM.